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WRITE A COUNTER IN VHDL

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koolslash

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vhdl counter

i want to write a counter in VHDL with following specs:
1. It read signal at a port from sensor
2. It count no. of pulses in 1 sec and then reset.
3. no. of counts are converted to 8'bit binary.


Looking forward for your help.ASAP:!:

Added after 1 hours 34 minutes:

I NEED IT FOR Final year Project and Need to submit within 1Week(Last week left for Report Submitting). So kindly help me ASAP....
 

sivarajm

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counter vhdl

Whats the problem in it dude.....
u find the rising edge of every pulse and start count for every rising of the pulse.
silmultaniously u run another counter.... to count upto 1 sec. If one sec readched then u initialise your counter.

Do u have any idea of what will width of the counter (no. of bits). If yes then u encode the bits from counter to 8 bits.
 

    koolslash

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koolslash

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counter in vhdl

if the frequency is 50MHz.
i get approx. 50,000,000 pulses in 1sec.
when i will read it from the sensor then and count them.
then how can i put this huge integer values on 8-bit binary scale.

means: 50,000,000 => '11111111'
00000000 => '00000000'

it works same as ADC. i.e. max volt to full scale reading.

SO ANY IDEA HOW WILL I DO THIS.
 

Marcel Majoor

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vhdl counter integer log

Counting to 50000000 during one second requires 26 bit.
Since you want a 8 bit result we only pass on the highest 8 bits, which is basically a 'div' operation.

result(7 downto 0) <= counter(25 downto 18)


Mind you, since 50000000 does not exactly fit in 26 bit (26 bit == 67 MHz full range) we do loose some range.
An exact 'scaling' is not advised here, although with some simple logic you might increase the resolution.
It would be better to transfer the result by some other means:
- higher resolution
- using fixed point 'arithmetic': bits for integer part and bits for after the decimal point (assuming this is needed)
- instead of measuring during one second, measure the time between two pulses (better: do both)

So, it all depends on the exact 'specifications'. Resolution, accuracy, etc...
Using 8 bits for the full range would have a resolution of 200 kHz steps ....
 

koolslash

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18 bit counter vhdl

CHECK THE FOLLOWING CALCULATIONS IS IT RIGHT:
period = 1/frequency
Period of board = 1/ 50MHz = 20nsec
If period is of 1ms: No of cycles = 1sec / 20nsec = 50,000,000 cycles.
My step delay equation will be: (16-bit input to PWM) (2^16)-1=65536
step delay = No of cycles/ 65536 = 762.9 approx=763

2^10 (10-bits) will cover 763 setps.
now what if i cover it most significant 8bits. How much accuracy i will lost??
 

Marcel Majoor

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vhdl counter with top

If period is 1 ms: No of cycles = 1 ms / 20 ns == 50000
(or 50 MHz / 1 kHz = 50 kHz)

If you want to control such with 8 bits (from 0..100%) then:
50000 == $C350 --> control will be high part so range from $00..$C3 -> note that the max PWM count could be set to $C300 (49920 -> 1001.6 Hz) to get a equal PWM spacing.

You then have a range of 0-$C3 (192) steps to set the PWM from 0..100%, so resolution is then 0.5% steps (100/192).
For an 8 bit range the smallest step obtainable are 0.39% steps (100/256).
16 bit: 100/65536 == 0.00152 %
etc...
 

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