Wrapper file - PC to FPGA communiction through PCI

[Ghostboy]

Wrapper

Hi,

I need to send data from a PC via PCI to the FPGA, where the data will be processed (videoprocessing-algorithm), and then sent the result to the PC via PCI.

I already generated the VHDL-code of the algorithm with "Xilinx System Generator" and also have the VHDL-code of the PCI-core.

Anyone who can give me tips for the making of the wrapperfile? Is this a seperate file (top-file) with the rest of the files under it? And does a wrapper has the structure of a FSM?
Or maybe someone who has an example of a wrapperfile?

Thanks in advance.

 

[Ghostboy]

Nobody who can just help me a little bit?
It's quite urgent actually!

Thanks

 

[afxx]

A wrapper file generally connects block A and B.

Your question is very vague. It's like asking "I need a VHDL file".

 

[Ghostboy]

Ok, I hope this version will be less vague

I want to send a video file from a pc to a FPGA (on a XUPV2P development
board) via the PCI interface. On the FPGA the video will be processed by an
algorithm. The result, after processing, will be send back to the pc. I
generated the VHDL-code of the algorithm in Simulink with Xilinx System
Generator (gateway_in and gateway_out are 8 bits wide). I also have the
VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the
algorithm in the PCI-code.

The resolution of the video is 320x240. The device driver on the pc (Linux)
gives an interrupt at the beginning of every frame. Can someone tell me how
I have to adapt the code of the user application delivered by Xilinx ( code
can be found here : **broken link removed** ) to give the
FPGA a sign to start processing the data and send the result back to the pc
after a frame has been processed? Is there a manner to check how many
bits/bytes/pixels passed by?

Thanks

 

[microKernel]

I'll download your code later in the day and may be able to help you. In general you system should work like this.

In FPGA, you'll need to implement the PCI slave device that will interface with PCI core and all of your algo should be in that part of the FPGA.
On the host side (Linux) you'll write a driver for that and on top of that an application that will send data to the slave device through PCI api provided by Linux and similarly get the data back on interrupt.
To signal the start of frame from application to the FPGA, you can use monitorying a buffer and for getting the data back you can use interrupts.

It is not fully clear from your description if you have tested your basic driver and the PCI device to make sure that it can generate interrupt which is handled properly.

 

[Ghostboy]

That would be nice.

I must admit that my knowledge of PCI is not so great.
The code I uploaded is only the code of the test application delivered by Xilinx.
But I presume it's in that file that I have to integrate the "gateway_in" and "gateway_out" of the algorithm along with the interrupts,... ?