working with scenarios...

[ee1]

Hi,
i have defineded some scenarios, and when i check timing and report_constraints of course i get different results for each scenario.
my question is, should i fix the violations for each scenario without considers the others?
and what is the recommended working method (for fixting violations with different scenarios)?

thanks in advanced!

 

[dhaval4987]

What exactly do you mean by scenarios? Do you mean operating conditions?

 

[ee1]

yes...
operating conditions, libs, tmp, power,,

 

[dhaval4987]

ok. generally what is done is- it is made work at 2 extreme conditions- that is SS and FF corners. (SS means, lower Vdd, Higher Vth and higher temperature and FF means higher Vdd, lower Vth and lower temp). So you should fix violations for this 2 extreme cases after you fix at typical conditions.

And then check SF and FS. Once you fix at any condition- you must check whether the same circuit with modification works at other corners or not.

 

[birdy123]

Hi,

Looks like you are using Primetime for this. but anyways .. the following concept is common to all the other tools.

As you mention about the sceniorio, I am not sure which technology are you using because the extreme condition like dhaval has mentioned are applicable for higher technology mode. but for lower technology these extreme conditions changes as per the path. Means it may happen that for a particular path in the design corner "A" and corner "B" are extreme conditions but for another path corner "A" and corner "C" are. So for a particular design , it may happen that more then 2 corners are signoff corners. So in that case, there should not be any violation in any of the voilation.

So best way is .. fix a particular violation at a particular sceniorio and cehck if it is not creating any violation in other corners.

different tools have different way of dowing this. In Primetime you can use DMSA feature , for solving this type of problem.

may be this much is useful for you. In case if you have any other question let me know.

 

[yadavvlsi]

Use slow libraries for setup time fixing and fast libraries for hold time fixing.. as hold time violations are due to faster data path and setup violations are due to slower data path.