working of SOC Encounter

[p_shinde]

hi,

SOC encounter does floorplanning, place and route and other things.

now it takes synthesized verilog file as an input, can that be the only input type.

as it does place and route so it should has standard cells, can we see them individually at mask layout level , out line is i want to how encounter works.


can we do place and route using standard cells in Virtuoso, if yes then onlly when we want to to go to fab without doing layout in practically , is it that time we use encounter????????


hope i framed the questions properly.

thanks in advance.

Prasad

 

[sree205]

i don't know about virtuoso. but, encounter works using algorithms which are part and parcel of every physical design tool. a good explanation of this has been given in both sherwani and sadiq sait.

i remember seeing at mask level, the standard cells of tsmc 35 um design from mosis website.

 

[arimilli_r]

Hi ,
For SOC encounter .v (syn netlist) is not only the input file.We have to give the LEF file which contains the abstract view of the cells used in the netlist file.

We cannot see cells in mask level , we can see in abstract level, i.e input and output pins and routing blockages and boundary of that cell. If we give the mask level info(GDS) the run time will be at task because of huge memory .

-Arimilli Rajesh.

 

[p_shinde]

hi,

here i am pasting some part of the .lef file, can anyone tell me whats that line of RECT and those numbers suggest?????????



PIN D
DIRECTION INPUT ;
PORT
LAYER METAL1 ;
RECT 3.080 1.845 3.085 2.075 ;
RECT 2.180 1.820 3.080 2.120 ;
END



thanks,
Prasad

 

[shankarmit]

you must know the difference of encouter and virtuoso

In encounter you import standard cells and netlist of your design..
the netlist contains standardcells and connectivity. between them..
thus encounter deals with place and route of this netlist..



In Virtuoso, the standard cells can be designed.it deals with basic transistor level..
there is no use in using standard cell library..

In encounter, will work in the level of blocks of standard cells and we dont go deep into transistor level..

 

[Ikon]

Mr P.Shinde,

Go thru the docs provided with the tool,if u want to know about the tool need to do some research on it, then u will know more points.

So plz go thru the docs, search the net u will find a lot.


Thanks