WLM & Gates Count

[ivlsi]

Hi All,

As for WLMs, how do they depend on Gates Count? How many WLMs are usually presented in *.lib files? How do they depend on the gates count of the design? Are there several WLMs, each one for is for different gate count and delay types (min/max/typ)?

Thank you!

 

[oratie]

As for WLMs, how do they depend on Gates Count?

It may depend on gate count. There are very many variants how WLM may look like. It depend on library vendor. How accurate WLM it offers.

How many WLMs are usually presented in *.lib files?

Again, depends on lib vendor. For example, I saw 5 WLMs (differ by design size) with pessimistic RC estimation, 5 WLMs with optimistic and one Zero WLM.

How do they depend on the gates count of the design?

They very depend on the gates count. As well as on aspect ration of the floorplan. The good solution is to create by yourself the WLM for your design. The best solution is to not use WLM, but use physical synthesis (logic synthesis with some kind of placement) - like Synopsys DesignCompiler topographical does. Instead of WLM, it does real placement of the gates, then calculate more or less accurate wire length, and then usung TLUplus files calculate the real RC values of the wires.

Are there several WLMs, each one for is for different gate count and delay types (min/max/typ)?

Yes, you may have different WLM for each gate count. Regarding PVT - the RC value variation have nothing with PVT. Yoy may have best case PVT (low Vt, low temp, high volt), but have worst case R (narrow wires and smaller thickness), for example. Usually, we have three PVT: best, worst and typical. And have 5 RC corners: typ, Cmax (C values are bad), C min (C is minimum), RC max and RCmin. We can not have both R and C values are worst, because, whe the wire is wider, the C is bigger, but R is smaller.