Within 1-2minutes plug in again, usb will work ,why?

[quan228228]

we have a chip which is used to capture data from sensor.

The chip works if not connect to sensor. When connect some sensor , the 1st time plug in won't work. But within 1-2minutes plug in again USb will work.

It is very strange.

Can anyone give some advice.
Thanks in advance!

/David

 

[vcnvcc]

Hi
As this is USb IP, it should be on fpga board as u r in testing phase, am i right?

which usb speed u r working with, i mean which device HS or FS??

How ur taking care of initial reset condition... I am assuming that u r working on device side... i.e. u r implementing device..

Added after 38 minutes:

And if u r working on HS...just check this out

considering ur device is self powered. n say u have connected usb cable to host port (means cpu usb port in simple words) so here ur initail reset from host comes into picture (i am taking abt initial reset betn host n device) so just check that CHIRP condition. u might have designed state machine with proper timings.....here timing is very imp....so according to clock freq u decide proper time.....

i think this helps u...

Regards.

 

[quan228228]

Thanks.
I know what you mean. You suspect that the usb detection process failed. This is an aspect.

Let me introduce more infor on testing. We have two type of package. one has 100 pins, the other has 64 pins. The 100-pin chip works correctly. but the 64-pin chip will be detected after successive plugging in twice(mean connect usb cable to host -pc).

I can't image , if the timing is wrong, why the 64-pin chip is detected after second plugging in.


Thanks in advance.

/David

 

[vcnvcc]

Hi,

Are you working on FPGA? You are loading that ip into fpga? or using asic, 64 pin ic and 100 pin ic?

See if you have designed that usb ip, and then you are testing it on fpga then this type of detection process comes onto picture.....Now why I am saying this because we faced same problem like you are facing.......

So if you have designed that ip just check timings between Device K and Host's KJ - KJ - KJ.......

Now your packages--- There may be possiblity that 64 pin package takes different time then that of 100 pin... so that is to be checked...this is my idea......

Vijay c.

 

[quan228228]

Now we are testing asic chip.

I agree with you. My friend said it is related to the manufacture. Maybe.

Thanks for your advice. I'll double check it.


/David

 

[vcnvcc]

Thanks David.

 

[quan228228]

vcnvcc:

We have solved the problem. The reason is that one input pin of 8051 are floating. The PCB engineer found this.

How about yours. Hope this can help you.

/David

 

[vcnvcc]

What we faced was design problem, Initial timing of our usb ip was not proper.