With the presence of assertions, how do cover groups help in verification?

[matrixofdynamism]

With power of assertions already present, how do cover groups help in verification?

SystemVerilog makes use of assertions and covergroups to achieve functional coverage. It is clear to me how assertions (as immediate and concurrent) help to verify a design and by basing them on design specification, it helps us to achieve functional coverage.

What is not yet clear to me is how do covergroups help in this process. As far as I understand, a covergroup simply counts how many times a certain event takes place during simulation, but it is not clear how such a count shall help in verification. It is possible that it is more than that.

What is a covergroup and how is it used to carry out functional verification?

 

[rberek]

Covergroups are useful when you are running a randomized set of regression tests. In these tests, you have seferal variables that take on a different value each time the test is run. For example, you may have a complicated block that has a lot of configuration registers that control that block's behaviour in simulation, so you randomize the contents written to the configuration registers every run and that test ensures that the block behaves as expected. Assertions are one of the tools that ensure this.

In the testbench the values you write into the config registers will be randomized on each test. You want to make sure that your randomized regression covers all of the values of these registers. So you assign covergroups to these configuration values. At the end of the regression run, if any covergroup shows 0 hits, you know your regression suite never tested those values. Therefore you will have to do something before the next regression run (i.e. add a test, modify a current test, or do more runs of some tests) in order to make sure those values are covered.

r.b.

 

[dave_59]

Please see https://verificationacademy.com/cookbook/Coverage