Will a CMOS gate consume power if its inputs are in hi imp.?

[vivek_p]

High Impedance-power

Will a CMOS gate consume power if its inputs are in a high impedance state? If yes, why?

 

[FvM]

Re: High Impedance-power

CMOS gate inputs can be expected to have high impedance by design.

If you mean unconnected respectively floating inputs, yes they can cause considerable current consumption of CMOS
gates (up to several mA). Refer to the circuit of a CMOS inverter and consider an input voltage of VDD/2. What's the state of
both input transistors then?

 

[karesz]

High Impedance-power

HI,
Undefined CMOS Input can cause "Latch-Up"s!
Some critical internal situation_ with illegal I/O voltage levels too(both FETs are conducting), in that case have a CMOS IC, as FvM wrote too, some mA (but at older types can be 100`s of mA + dangerous for the IC self)...
K.

Added after 2 minutes:

Other problem of open CMOS-inputs is: a fully uncontrollabe function of your IC, becouse if you tip it witha probe=you have a high, but fix resitor at thes point_and this do charge/decharge(!