Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why zero hold time is prefered?

Status
Not open for further replies.

yuhiub90

Member level 2
Member level 2
Joined
Aug 2, 2012
Messages
52
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Hanoi, Vietnam, Vietnam
Visit site
Activity points
1,618
I've read an article said that today's libraries tend toward rising-edge active clocks, zero hold times, and positive set-up times. So why zero hold time is prefered to positive hold time?
Thank you.
 

Well it is always a trade-off between the logic you add to increase the hold time margin. So the minimum is zero hold time, but if with adding "few" std cells, you could increased the hold time margin, then, you are in safe side.

The hold time distribution will show you how much path are close to "zero" and then how many std cell is needed to increase your margin.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top