Why will at low temperature Corner point Analysis( in cadence Virtuoso) fails?

[Ali263]

I am doing corner point analysis of my design for all process corners and at different temperature.
However one amplifier fails at low temperature set? What can be the reason and how can it be fixed? In attach files, one can see the close loop, internal 2 stage OTA and its close loop gain. For corners at -10 temperture it fails.

How can i fix it?

 

[arthorios]

Show schematics, testbench and conditions for the simulation. Then, maybe, someone can have some insight.

 

[Ali263]

is

Show schematics, testbench and conditions for the simulation. Then, maybe, someone can have some insight.

is it ok now? I have attached snaps

 

[sutapanaki]

Why don't you check the operating point of your transistors in that specific failing corner?

 

[arthorios]

Not enough, but close. So I will only guess.

You are using only one CMFB to set and sense the output CM level while controlling the 1st stage current sources. This is okay, but the problem you might have is that you leave the 1st stage output CM level dependent on the inversion level of the output stage transistor (PMOS here). So it might happen that the output CM of the 1st stage need to be too high/low to set the required VDD/2 at the output.

I would check what is the vgs-vth of the PMOS output transistors under failed corner. If this is too large, then give it more margin. Do simple DC op sims to debug this.

 

[Ali263]

Why don't you check the operating point of your transistors in that specific failing corner?

I have a big chain and i check entire chain for 36 corners but only this amplifier fails for negative temperature.
can you explain how should i check OP when it is connected in closed loop .

 

[sutapanaki]

Checking the OP in closed loop is not an issue. It is actually easier than doing it for the open loop case. It doesn't look you have a switched-capacitor circuit, so just enable DC analysis in cadence and print or annotate the operating point on the schematic. Do one simulation only for the corner that gives you trouble.

 

[dick_freebird]

It looks like bias is simple so not the common
"my PTAT won't start up" problem.

There is always the possibility that some
corner or other is garbage from the foundry
modeling group. I've fought this a lot when I
was "inside foundry" and forced to run MC
analyses - would get runs where some
device(s) can be shown to fail WAT limits,
and the CAD weasels care not one bit.

The only way forward was to document
all of the fails-WAT MC iterations (which
were thankfully -not- random, but
pseudorandom repeatable from the same
seed any time you like), and disposition
any fails from those while running enough
extra iterations to mollify the Methodology
Harpies.

I would suggest that you lash up a fake
"WAT key" schematic imposing the major
WAT tests and ones that might matter to
an op amp (like FET Rout, which is seldom
measured other than as Vgs=0 leakage),
and see what "breaks out" for transistor
attributes at your failing iteration(s).

Now if it all goes out at low temp, processing
aside, that's probably something more basic.
Like maybe your VT has risen enough that
you have no headroom and thus no gain.

Scatter-plotting failing circuit attribute vs
the device characteristics you pulled from
that "WAT key" simulation (because of course
you followed my advice) might point you at
a highly-correlated suspect, and you could
decide whether normal processing or only
unrealistic parameter perturbations can
cause the failure.