Why we usually let input stage voltage as vdd/2 ?

[shaq]

Dear all,

When we perform a pre-layout simulation of open-loop gain and phase margin, ususlly let input stage voltage as vdd/2.

Why do we need to choose vdd/2, not another value such as 2v,1v whatever ?

 

[watersky]

your idea is allowable. If your use is 1V nearly, 1V can be used. usually choosing vdd/2, it is a reason that it can obtain max sine fluctuation.

 

[jerryzhao]

Yes, use vdd/2 can obtain max sine fluctuation. But you should check the input common mode voltage efect of your op. At that time you should do AC simulation use different input VCM.

 

[wang.yuanzhuo]

i think you could choose another voltage,the best choice let your input swing achive largest.

 

[Areky_qin]

vdd/2 is for the max difference input range, with this setting, you opamp can be work well. of cource you should vary the common mode input voltage to check your circuit's common mode as jerryzhao
said.

 

[paladinzlp]

sometimes, the vdd/2 isn't the best value of the input.It is decided by the best operation point.