seriously it needs pictorial explanation.In clock gating using latch, we are still ANDing CLK with CLK_ENABLE signal, but not directly. As explained above, if we simply AND CLK_ENABLE and CLK, then in the actual design CLK_ENABLE may come from combinational path with varying delay which if deasserted during high cycle of CLK, then the output of AND will be clipped clock. This may cause problem in the design.
Now, using latch we can fix this issue. Simply feed CLK_ENABLE to the input to the latch, and feed the clock to the active low enable input of the latch. AND the output of the latch with clock.
The latch is transparent only when CLK is low, otherwise opaque. When CLK_ENABLE is low, the output of latch and AND gate is always low. This means clock is 'gated'. Now, what happens if CLK_ENABLE is high? the output of AND gate doesn't go high immediately because latch is opaque during high cycle of clock. Only when clock is low, CLK_ENABLE is pass through the latch the AND gate. When clock goes back to high cycle, since CLK_ENABLE is already asserted, there is no chance of clock clipping.
I hope this helps.