MBIST circuit generated by Vendor is mostly in RTL. ( at least Mentor )
The input of MBIST insertion is either RTL or NETLIST designs.
It means that, there will be 1 more compile time after MBIST insertion.
SCAN inserted circuit however, mostly in NETLIST designs. ( as far as I known)
There is theorically no additional complie is required after SCAN insertion.
Hence, it is a practical reason that the general flow should be:
Initial compile -> MBIST circuit insertion -> additional complie -> SCAN insertion (-> additional compile 2 [optional])