Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why we dont consider the hold time of source flip-flop for calculating max. frequency

Status
Not open for further replies.

sujittikekar1

Junior Member level 2
Joined
May 16, 2007
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,465
can anybody tell why we dont consider the hold time of source flip flop while calculating max. frequency?
 

Re: maximum frequency

bcoz while calculation we consider "clock to Q" time of flop which automatically includes "hold time" ( as almost all the time clk-to-Q > hold_time)....

so eqn is like
Code:
  f = 1/(clk_to_Q + prop_delay + routing_delay + set_up_of_next_flop)

something like this....

P.S. : clk_to_Q itself includes hold time
 

Re: maximum frequency

Hold time is some thing that affects the performance only after the clock arrives... so we have to only cosider only the computational delay of the circuit...
 

maximum frequency

I think that hold time does not affect the maximum operating frequency you can work with at all. It sets a limit for the minimum allowable clock-to-Q and propagation delays , such that Tcq+Td > Thold.
ALso it puts a limit on the skew between CLK at different clocked elements.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top