why we are going for scaling of CMOS technology and what are their limitations

[rameshiloveu]

why we are going for scaling of CMOS technology and what are their limitations ?

 

[Prashanthanilm]

Hi Ramesh,

Scaling down means reducing the sizes of a transistor. Since if the size of a transistor is reduced , the no of transistors in a IC will be more.
Scaling follws the pace with which MOORE has described.

Below are the few process with problem and solution:

Process Problem Solution
180nm Conductors become too resistive Replace alum. with copper
130nm Features smaller than light wavelength Computational lithography*
90nm Limitations on active current Strained silicon
45nm Gate leakage limits scaling Hi-K metal gate
22nm Loss of channel control Tri-gate transistor

There are lot of articles in the internet on the same , you can explore.

 

[timof]

why we are going for scaling of CMOS technology and what are their limitations ?

1. reduced power dissipation
2. increased transistor density (i.e. more transistors per unit area)