Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
yes, what adap mentioned is what we also called "synthesizable verilog code". at RTL level, logic change depends on the clock for synchronize design. there is another level called behavirol level, in this level you just describe how ur design may function, it doesn't have to be in logic and register level, hence it's not synthesizable code.
verilog can be used for RTL description in front end design, besides, verilog can be for behavial description, extent to a good verifacation language via PLI, and many netlist can be in a verilog format.