why V0/Vi is less than unity gain if RL is finite?

[wjxcom]

less than unity gain

Hi, all: look at this circuit please. In this circuit, as Vi decrease from the value that forces V1=0, V1 increase and V0 follows but with less than unity gain if RL is finite.

I do not know why there have less than unity gain if RL is finite?

Help me, Please!!

 

[jlee]

Do you mean Vo/Vi < 1, or Vo/V1 < 1 ?

From what I see, the left half of the circuit is a class-AB output stage. The right half of the circuit is unity-gains stage. Combining as a source-follower output stage, the output voltage Vo tracks V1. When the loading RL is finite, there will be current flowing through RL. This current is supported by M1/M11, or M2/M22. More current through transistors means a bigger Vdsat. Therefore, when V1 increases, Vo doesn't increases as much as V1 due to the bigger Vdsat. So the gain is a little bit < 1 .... actually it should be very close to 1.

On the other hand, Vo/Vi does have gain... gain can be > 1.

 

[wjxcom]

Hi, jlee: you said that "The right half of the circuit is unity-gains stage", would you explain detailed why?

thanx you!!

 

[mists]

also please refer gray's book for class ab output stage, it is on about page 390.

 

[wjxcom]

hi, mists: in fact, this circuit is the output stage that introduced in Gray's book. And Gray does not say why "as Vi decrease from the value that forces V1=0, V1 increase and V0 follows but with less than unity gain if RL is finite. "

 

[pixel]

In the input part of the circuit there are PMOS and NMOS branches in source follower configuration to the output (for M1,M2 signal flows from gate to source).
Source followers with NMOS have bulk-effect problem, which results in NMOS source follower gain less than 1.

 

[montage2000]

because of internal resistor