why using non-ideal clock to simulate the circuit

[mike0426]

I wonder that what's the difference between ideal clock & non-ideal clock(generate by osc).
I heard that ideal clock may make us ignore some effect which using non-ideal clock would appear,but I'm not sure the reason and what the effect is.
Hope someone know this can anwser this question.
Thanks a lot

 

[mladen_haj]

Basically, all the clocks in reality are non-ideal one. There are at least two effects which could be observed by non-ideal clock. First one is the fast instability of clock which is described primarily as phase jitter causing phase fluctuations in the circuits we design. The second one is long term instability mainly causing frequency drift.
Regards,
Mladen

 

[dick_freebird]

You would want to challenge circuit aspects that
depend on clock ideality - duty cycle causing errors
in sampling / chopping circuits, overlaps causing
sample pedestal error, short duty equating to short
setup time within a cycle, etc. Observing the results
of an ideal clock is all well and good. Believing them,
not so much. You have to falsify the hypothesis to
test the theory.

 

[leo_o2]

One of difference in my brain is the driving capability difference. Non-ideal clock has limited driving capability.

 

[mike0426]

Thank you for your answers! But I still have a question, how non-ideal clock would limit driving capability? Can someone explain it in detail?

 

[leo_o2]

Non-ideal clock driving capability is limited by output resistance of driver.
In practical design, output resistance will not be zero. And voltage source also has some output resistance too.