Why Use FPGA's for Oscilloscopes?

[rockom]

I posted this last night and I either posted in the wrong thread or it was moved.
Hobby Circuits and Small Projects is where I wanted it so....lets try again.

I've been scouring the web looking at different homebrew oscilloscope solutions and have found ALL of the projects that are capable of greater than a few hundred kHz are using an FPGA or CPLD.

Why is that? What would a uC need to offer in order to fill this block of the designs?

Thanks,
-Rocko

 

[banjo]

To make an oscilloscope using a microcontroller and have a high bandwidth, you need a microcontroller with a very high clock rate. Microcontrollers are just not up to that task. FPGAs or CPLDs can be clocked at a high enough rate to get decent bandwidth. Even with FPGAs or CPLDs the problem is limited capture depth because their internal memory is limited. You can add external memory, but it also has to be very fast or again bandwidth goes down.

 

[Mehdi1357]

Hi
by using a ADS831E(8-Bit, 80MHz Sampling ADC),XC95288(Xilinx's CPLD) and an external 32K*8bit FIFO you can Make a DSO up to 80M sampel per second.
I am not in love with any microcontrollers (even Arm9)!!!

 

[rockom]

Hi
by using a ADS831E(8-Bit, 80MHz Sampling ADC),XC95288(Xilinx's CPLD) and an external 32K*8bit FIFO you can Make a DSO up to 80M sampel per second.
I am not in love with any microcontrollers (even Arm9)!!!

I guess I should try playing with an FPGA or CPLD. Never used one.

I though a 40+MHz ADC, OMAP3530(BeagleBoard), and a ridiculous amount of high speed RAM (DRAM?) might be cool. The OMAP would also handle an LCD.

-Rocko

 

[Aser]

FPGA would be better
because it contains built-in RAM.
The RAM volume is enough to store the rather long signal trace with the high speed.
Therefore the additional RAM chips are needn't.
Moreover,
new FPGA contain high speed serial-to-parallel input blocks
which provide the data sampling with up to several MHz frequency.

 

[Mehdi1357]

FPGA would be better
because it contains built-in RAM.
The RAM volume is enough to store the rather long signal trace with the high speed.
Therefore the additional RAM chips are needn't.
Moreover,
new FPGA contain high speed serial-to-parallel input blocks
which provide the data sampling with up to several MHz frequency.

Hi
I agree with you Wholeheartedly a FPGA reduces PCB wires and is a beter technique rather than a CPLD and external Fifo.
but the expenses will increase.