Why use double inverter gate ????

[Elits]

Hi all,

I ever see digital schematic design that using double inverter just to transfer logic 1, What is the purpose? Why not direcly connected? is this metode has relationship with increasing the current or power of logic 1?

thanks.

Elits

 

[checkmate]

It's used in some counters as a delay component to resolve data races.

 

[eltonjohn]

there are several uses of that practice .One is just as a current buffer .You want to pass the same logical state as at the input ,but being able to drive something .Another use is to shape up a signal .some logical pulses are not really straight on the edges and not predictible when to switch so to "make it more logical looking" and give it a real timing yoy want to shape it with inverters .This is often the case with oscillators.
Finally another is when you want to elevate or lower the voltage with Cmos logic !

 

[dBUGGER]

Hi,
It is primaly used to buffer the signal for high current requirement. It prevents the signal from being distorted. There are some inverters with hysteysis o/p, So this shapes up the signal as well.

Best Regards,

 

[jeffttan]

it can be used for delay, another use for it is to "refresh" the signal from the output of the gate connected to the double inverter.

 

[elecomm]

It is in most cases used as a buffer to be able to drive large capacitive load like for example the pins of the IC package you may use cascaded inverters in order to buffer the signal to the output

 

[SkyHigh]

Double Inverter Gate sees several applications:

1. To drive a high capacitive load. CMOS inverter found in digital logics uses minimum sized transistor, thus not capable of driving such load. It will take a long time to charge such a load or discharge a load using a minimum sized transistor (which can suffer from punch-through). One way is to use multiple buffer chain or cascaded inverters. Double inverter is one such example. The second and subsequent inverters are designed to have larger transistors carefully scaled such that the low-high transition time or high-low transition time is fast (fast gate propagation delay). This also reduces duration of short-circuit current when CMOS inverter switches and also gives a steeper edge.

2. Domino logic uses an inverter in dynamic CMOS logic. This inverter is a latch preserve the previous logic value. If the prior logic is an inverter used in Domino logic, than this can be referred to as double inverter.

3. In random logics where 74-series ICs are used. Double inverter gates are used to increase the fan-out of a driver, which can be TTL, ECL, Open-collector, Open-drain etc. Usually bus drivers might need to drive more than one signal lines and double inverter is used to increase fan-out while preserving the same logic value by double inverting.