Why use a DLL to generate a clk?

[stanford]

DLL only generates a delayed version of a reference clk.

Why can't we just use a chain of inverters to delay the clk? Seems more simple this way.

 

[FvM]

DLL delay is independent of process, voltage, and temperature (PVT) variations.

 

[jihrenee]

DLL is a negative feedback system, while a chain of inverters is an open loop system.
So DLL is more robust to PVT variation.
For example, when the supply voltage is increased,
the generated clock of DLL can be still maintained at the same phase, although the delay from the delay line is smaller.
(Assume the delay variation is still in the delay range)

 

[dick_freebird]

It all depends on whether you want your delay controlled
(loop-locked) or not. The less you demand, the simpler it
can be.

 

[stanford]

Wouldn't the PVT variation affect the DLL circuit too (i.e increase in supply voltage directly decreases the delay circuit)?

Plus, if the ref clk has variations, you are just delaying the ref_clk that already has variations. I don't see how DLLs helps with variation...

 

[FvM]

DLLs are e.g. used to generate a clock that's 90 degree phase shifted relative to an input clock. Relative means that the phase "variations" of the input clock are irrelevant. Phase shifted clocks are often needed for DDR RAM interfaces.

There are basically two DLL concepts

- delay compare and select (the pure digital method)
You have a tapped delay chain with a propagation delay of at least one clock period. It's continuously determined how many delay stages correspond to a full clock period, then 1/4 of it is used for the 90° output
- delay control (the classical analog method)
You have a voltage or current controlled delay chain with continuously variable delay. It's controlled in a close loop to match a full clock period. Then the taps have a constant delay relative to the clock period.