maninnet
Member level 5
in an opamp design, some of the transisters' widths are big that (in the range from
60u to 200u in tsmc0.35 process) i set fingers for all of them in cadence, and i expect parasitic will be reduced such that unity gain frequency will be improved, but the simulation yields the same result, could anyone share some experience?
60u to 200u in tsmc0.35 process) i set fingers for all of them in cadence, and i expect parasitic will be reduced such that unity gain frequency will be improved, but the simulation yields the same result, could anyone share some experience?