JKR1
Junior Member level 3

I wrote a testbench for my code but while elaborating the design I have this error
here is the entity :
and here is the component :
I would appreciate if somebody help me.
but types of the component and the entity are the same,I dont know why this error is happening???# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_in".
# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_out".
here is the entity :
Code:
entity x1 is
generic (m,n : Integer := 64);
port(clk : in std_logic;
p_in : in unsigned(7 downto 0);
p_out : out unsigned(7 downto 0));
end x1;
Code:
COMPONENT x1
PORT(
clk : in std_logic;
p_in : in unsigned(7 downto 0);
p_out : out unsigned(7 downto 0)
);
END COMPONENT;