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why to remove hierarchy in physical syn?

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manivannanrm

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why we have to flatten the logic data while starting physical synthesis?
if not flattend what happens ?
tnx in advance

manivannan
 

semi_jl

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Hi,
If you do it with Physical Compiler, I don't think the design is flat, but the tool use clusters replace the hierarchy in order to create floorplan.
 

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