gauz
Junior Member level 3
Hi, Everyone
I implemented my design in xilinx spartn3, PAR is ok, no timing violation reports after STA, but when I run timing simulation with the simulaltion file generated by ISE, the X_FF(which is a cell in lib simprims_ver) report setup and hold violation.
I am puzzled and don't know why it happens, Could anyone give me any ideas???
Thanks so much!
gauz
I implemented my design in xilinx spartn3, PAR is ok, no timing violation reports after STA, but when I run timing simulation with the simulaltion file generated by ISE, the X_FF(which is a cell in lib simprims_ver) report setup and hold violation.
I am puzzled and don't know why it happens, Could anyone give me any ideas???
Thanks so much!
gauz