why this warming with project of VHDL?

[chxgzl4862]

ise 10.1 warning:xst:1780

hello, everybody.
my project is
entity IIC_FSM is
------------------------------------------
port (
IIC_FSM_CLKIN: in std_logic;
IIC_FSM_RST: in std_logic;
IIC_FSM_CS: in std_logic;
-- IIC_FSM_STATS_CS: in std_logic_vector ( 3 downto 0 );
IIC_FSM_NUM: in std_logic_vector ( 7 downto 0 );
IIC_FSM_ECLK: out std_logic;
IIC_FSM_IICCLK: out std_logic
);
------------------------------------------
end IIC_FSM;

architecture Behavioral of IIC_FSM is
------------------------------------------
component IIC_CLK
port (
IIC_CLK_CLKIN: in std_logic;
IIC_CLK_RST: in std_logic;
IIC_CLK_CS: in std_logic;
IIC_CLK_DIVH: in std_logic_vector ( 3 downto 0 );
IIC_CLK_DIVL: in std_logic_vector ( 3 downto 0 );
IIC_CLK_ECLK: out std_logic;
IIC_CLK_CLK: out std_logic
);
end component;
------------------------------------------
------------------------------------------
signal IICFsmClk: std_logic;
signal IICFsmClkFlag: std_logic;
--signal IICFsmSdaIn: std_logic;
signal IICFsmSdaOut: std_logic;
--signal IICFsmStartSdaOut: std_logic;
--signal IICFsmStartSckOut: std_logic;
--signal IICFsmStopSdaOut: std_logic;
--signal IICFsmStopSckOut: std_logic;
--signal IICFsmWriteSdaIn: std_logic;
--signal IICFsmWriteSdaOut: std_logic;
--signal IICFsmWriteSckOut: std_logic;
--signal IICFsmReadSdain: std_logic;
--signal IICFsmReadSckOut: std_logic;

signal IICFsmClkCnt: std_logic_vector ( 3 downto 0 );
signal IICFsmPaseReg: std_logic_vector ( 3 downto 0 );
--signal IICFsmStatsnCS: std_logic_vector ( 7 downto 0 );
------------------------------------------
begin

IIC_FSM_CLK: IIC_CLK
port map (
IIC_CLK_CLKIN => IIC_FSM_CLKIN,
IIC_CLK_RST => IIC_FSM_RST,
IIC_CLK_CS => IIC_FSM_CS,
IIC_CLK_DIVH => IIC_FSM_NUM ( 7 downto 4 ),
IIC_CLK_DIVL => IIC_FSM_NUM ( 3 downto 0 ),
IIC_CLK_ECLK => IIC_FSM_ECLK,
IIC_CLK_CLK => IICFsmClk
);

IIC_FSM_IICCLK <= IICFsmClk;

IIC_FSM_PASE:
process ( IIC_FSM_RST,IIC_FSM_CS,IICFsmClk )
begin
if ( IIC_FSM_RST = '0' ) then
IICFsmClkCnt <= "0000";
IICFsmClkFlag <= '0';
IICFsmPaseReg <= ( others => '0' );
elsif ( rising_edge ( IICFsmClk ) ) then
if ( IIC_FSM_CS = '0' ) then
IICFsmClkCnt <= IICFsmClkCnt + "0001";
case IICFsmClkCnt is
when "0000" =>
IICFsmPaseReg <= "0000";
IICFsmClkFlag <= '1';

when "0001" =>
IICFsmPaseReg <= "0001";
IICFsmClkFlag <= '0';

when "0010" =>
IICFsmPaseReg <= "0010";
IICFsmClkFlag <= '0';

when "0011" =>
IICFsmPaseReg <= "0011";
IICFsmClkFlag <= '0';

when "0100" =>
IICFsmPaseReg <= "0100";
IICFsmClkFlag <= '0';

when "0101" =>
IICFsmPaseReg <= "0101";
IICFsmClkFlag <= '0';

when others =>
IICFsmPaseReg <= "0000";
IICFsmClkFlag <= '0';

end case;
else
IICFsmClkCnt <= "0000";
IICFsmClkFlag <= '0';
end if;
end if;
end process IIC_FSM_PASE;

end Behavioral;

i use ise 10.1
but,i compile it there is some warming
WARNING:Xst:2677 - Node <IICFsmClkCnt_3> of sequential type is unconnected in block <IIC_FSM>.
WARNING:Xst:2677 - Node <IICFsmClkCnt_2> of sequential type is unconnected in block <IIC_FSM>.
WARNING:Xst:2677 - Node <IICFsmClkCnt_1> of sequential type is unconnected in block <IIC_FSM>.
WARNING:Xst:2677 - Node <IICFsmClkCnt_0> of sequential type is unconnected in block <IIC_FSM>.

i want to deal with this warmning,what can i do!

 

[Marcel Majoor]

vhdl unconnected signal

Without the code for IIC_CLK we can't reproduce the same result you are having.
Without the IIC_CLK code I don't get the warnings you indicate, but I do get others like:
WARNING:Xst:1780 - Signal <IICFsmSdaOut> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IICFsmPaseReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IICFsmClkFlag> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

which have to do with the missing code ...

 

[chxgzl4862]

vhdl block is unconnected

hi!
i have this warming also!,i delete it!

 

[devas]

Hi,

What do you mean with "delete it"? Do you ignore these warnings?

Due to the three warnings, Marcel mentioned already, this part of your code has been optimized (removed from the logic). These signals depends on the output of the counter, so the counter output has no logic anymore behind it.

When you add one of the signals, depending on the counter output, the port list as an output port, and you recompile it, the warning about the counter output should not appear anymore.

Devas

 

[chxgzl4862]

hi!
"delete it" is mean i delete it,i have this warning to with compile it!
i mean it why great this warning! i try again!
thanks!