why this nor decoder has glitch on its output?

[leohart]

I bulid a 5 to 32 nor decoder(takes 5 binary and their compliment as its input to enable one of its 32 output ) myself and simulate using spectre, but I found its output includes strange glitch on some of its output node(they are all mulitples of 4,like 32,28,24...).

I just use a multiple divided by 2 clk and compliment as the decoder's input,pls check out the plot for me...thank you

 

[leohart]

I find the problem roots from the slight asynchronous of the rising/falling edge of the input clock,how can I eliminate this?

 

[A.Anand Srinivasan]

post your circuit... seeing the circuit you've used only timing problems like this can be analysed....

 

[leohart]

this is the simplified 3-8 nor decoder


I think the glitch is called static hazard in digital design...but just dont know how to eliminate them,maybe this is not the end of the world for me because I'm using synchorus circuit.

 

[leohart]

ps: the gate of pmos is connect to a precharge clk in this sch,but I just connect them to gnd cause I'm using it as a combinational logial rather than a sequential one.

 

[A.Anand Srinivasan]

post the clock waveform and input waveforms... the problem is due to the timing difference between the input waveforms only... the precharge cycle is generally used to avoid problem due to difference in the arrival of the input signals...