why this line have a syntax error in modified booth multiplier code?

[fahim1]

hi
i write the modified booth multiplier code like this...
I defined the signals but it has a syntax error ,I dont know why??
in the for loop if I want to do this for i=0 and i=2,did i express it correct?
for i in 0 to 2 loop
.
.
.
i=i+2;
end loop;
--------------code-----------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
entity mdboothmul is
port(mpcd,mplr : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
--------------------------
architecture mdboothmul_arch of mdboothmul is
signal acc : std_logic_vector(7 downto 0):="00000000";
signal tmpcd : std_logic_vector(7 downto 0);
tmpcd(7 downto 4) <= (others => '0'); ---???
tmpcd(3 downto 0) <= mpcd;
signal tmplr : std_logic_vector(4 downto 0);
tmplr <= mpcd & '0' ; ---??
begin
process(clk)
--variable tmpcd : std_logic_vector(7 downto 0);
--tmpcd(7 downto 4) := (others => '0');
--tmpcd(3 downto 0) := mpcd;
--variable tmplr : std_logic_vector(4 downto 0);
--tmplr := mpcd & '0' ;
variable temp : std_logic_vector(7 downto 0):="00000000";
begin
if (clk'event and clk='1') then
for i in 0 to 2 loop ---?
if (tmplr(i+2 downto i) = ("000" or "111")) then temp := "00000000";
elsif (tmplr(i+2 downto i) = ("001" or "010")) then temp := tmpcd;
elsif(tmplr(i+2 downto i) = "011") then temp := tmpcd(6 downto 0) & '0';
elsif(tmplr(i+2 downto i) = ("101" or "110")) then temp := tmpcd(6 downto 0) & '0';
elsif (tmplr(i+2 downto i) = ("101" or "110")) then temp := not(tmpcd)+'1';
elsif (tmplr(i+2 downto i) = "100") then temp := not(tmpcd(6 downto 0) & '0') + '1';
end if;
i:=i+2; ---??

end loop;
acc <= acc+temp;

end if;
end process;
result <= acc ;
end mdboothmul_arch;

if someone have another code for modified booth multiplier code,I would appreciate if put it in the comments...
thanks

 

[shaiko]

tmpcd(7 downto 4) <= (others => '0'); ---???

Signal assignment isn't allowed in the signal declaration section.
Only after the "begin" of the architecture.

 

[TrickyDicky]

You also cannot modify a loop variable inside the loop - the loop var is considered static and cannot be modified - it increments deending on the range you set. So it goes 0,1,2 in that order. If you specified 2 downto 0, it would be 2, 1, 0.

Anyway - Your code looks too much like a software program that will generate a lot of logic. this will result in a slow maximum frequency. Why not simply pipeline the algorithm without a loop?

I also recommend you dont use variables!

 

[fahim1]

You also cannot modify a loop variable inside the loop - the loop var is considered static and cannot be modified - it increments deending on the range you set. So it goes 0,1,2 in that order. If you specified 2 downto 0, it would be 2, 1, 0.

Anyway - Your code looks too much like a software program that will generate a lot of logic. this will result in a slow maximum frequency. Why not simply pipeline the algorithm without a loop?

I also recommend you dont use variables!

thanks TrickyDicky,I changed the whole code and starting to write a new code for modified booth multiplier,but in advance I have a problem I WANT TO define negetive range for example

signal a :std_logic_vector(3 downto -1);

but it has error.will u please help me what can I do?

 

[TrickyDicky]

You cant use a negative range for std_logic_vectors. You have to use positive only.
Why do you want to use -ve anyway?

 

[fahim1]

I decided to write it according to this block diagram(because you said the last code was behavioral)
note that m=2i
according to the booth algorithm if we attach 0 to the lsb of the Y.before Y was (3 downto 0) now its Y&'0'
IF I assume that they are 4 bit
when i WANT TO WRITE the loop I can write

for i in 0 to 1 loop
dir := Y(2*i-1);
sht := Y(2*i);
add := Y(2*i+1);

I will have two partial products ,for the first (i=0) it is defined correct .
but if i put it from 0,i cant have this.

- - - Updated - - -

i write this code now

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
entity mdbooth is
port(mpcd,mplr : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
--------------------------
architecture mdbooth_arch of mdbooth is
signal tmpcd : std_logic_vector (7 downto 0);
signal tmplr : std_logic_vector (3 downto -1);
signal nottmplr :std_logic_vector (3 downto -1);
signal acc : std_logic_vector(7 downto 0);
begin
nottmplr <= not(tmplr)+1 ;
process(clk)
variable dir,sht,add : std_logic :='0';
variable a,b,c : std_logic_vector(7 downto 0);
variable temp : std_logic_vector(7 downto 0);
begin
if(clk'event and clk='1') then
for i in 0 to 1 loop
dir := mplr(2*i-1);
sht := mplr(2*i);
add := mplr(2*i+1);
case dir is
when '0' => a := tmplr;
when others => a := nottmplr;
end case;
case sht is
when '0' => b := "00000000";
when others => b := a&'0';
end case;
case add is
when '0' => temp := b;
when others => temp := a;
end case;
end loop;
end if;
acc <= temp+acc;
end process;
result <= acc;
end mdbooth_arch;

 

[TrickyDicky]

I dont think you quite understand what a for loop does - when it is synthesised, it unrolls the loop and creates parrallel hardware. Your code still looks like software.

I highly suggest you re-write the code - this time with no loops and no variables.

 

[FvM]

I dont think you quite understand what a for loop does - when it is synthesised, it unrolls the loop and creates parrallel hardware. Your code still looks like software.

Furthermore, in the present code nothing is unrolled, the second iteration overwrites the result of the first. It's just a useless loop.

 

[fahim1]

I dont think you quite understand what a for loop does - when it is synthesised, it unrolls the loop and creates parrallel hardware. Your code still looks like software.

I highly suggest you re-write the code - this time with no loops and no variables.

hi TrickyDicky,thanks for answering,unfortunately I dont know about synthesizer,I just learned vhdl from some books and they didnt mentioned anything about synthesizer, I would really appreciate if u help me what can I do to get that point of view for writing codes.
and for the program variables should be replaced with what?and whats wrong with using variables/.??
and the loop is because its a four bit multiplier, two partial products should be produced with this loop.
I dont understand why is this software i just used 3 multiplexers??
thank u

- - - Updated - - -

Furthermore, in the present code nothing is unrolled, the second iteration overwrites the result of the first. It's just a useless loop.

why overwrite??
the valu in the loop is stored in temp and at the end of the loop it will be added to the acc which is having the previous sum.

 

[FvM]

temp is set in each iteration. Only the last value is kept, so any calculation result from previous iterations is lost.

 

[ads-ee]

I would really appreciate if u help me what can I do to get that point of view for writing codes.

Knowing digital design and knowing how to draw a schematic before writing code would be the right point of view. If you can't describe the circuit using a schematic you shouldn't be writing code (this is why most software types write bad VHDL/Verilog descriptions, because they start by designing the code, without designing the hardware first).

and for the program variables should be replaced with what?and whats wrong with using variables/.?

why? ... this is why.

temp is set in each iteration. Only the last value is kept, so any calculation result from previous iterations is lost.

For loops in software are temporal (sequences in time), for loops in HDLs are spatial (parallel copies with different indices).

Until you really understand VHDL you should only be using signals and no for loops. When you have that mastered then add for loops followed by variables (and you only need to use those sparingly)

 

[fahim1]

Knowing digital design and knowing how to draw a schematic before writing code would be the right point of view. If you can't describe the circuit using a schematic you shouldn't be writing code (this is why most software types write bad VHDL/Verilog descriptions, because they start by designing the code, without designing the hardware first).


why? ... this is why.


For loops in software are temporal (sequences in time), for loops in HDLs are spatial (parallel copies with different indices).

Until you really understand VHDL you should only be using signals and no for loops. When you have that mastered then add for loops followed by variables (and you only need to use those sparingly)

some algorithms are too big and its impossible to draw aschematic and write the code according to it,in these cases what can I do?
and assume that I wrote A code how can I find that its behavioral or structural??
thanks

 

[TrickyDicky]

some algorithms are too big and its impossible to draw aschematic and write the code according to it,in these cases what can I do?
and assume that I wrote A code how can I find that its behavioral or structural??
thanks

No algorithm is too big - it might be broken down into different layers of hierarchy, but you MUST draw the architecture of the algorithm before you write the code for it. Without doing that, it's just anarchy and a mess, and just increases integration time.

Engineering is not about writing code - its about writing documentation.