Why there are different TSMC rules for metal widths ?

[Raptor]

DRC Rule Question

I have a question about metal widts. Below is the description.
In tsmc foundry rules the min metal widts are
Mt1=.23,Mt2-Mt5=.28 and Mt6=.46

why widts r const for mt2-mt5 and why it changes for mt1 & mt6. only

 

[nathan]

Re: DRC Rule Question

Hi,

M1 width is the smallest one since it's going to limit your transistor density and it is used for intra-cell routing. The upper one, in general it is used for global power distribution and is thinker than the others, therefore, you cannot achieve smaller width.
In the middle the minimum width is fixed by your litho system capabilities.

Very often the material is different for M1 and the rest (i.e., M! is more resistive than the others) as well as for the uppermost metal and the rest (i.e., less resistive)

nathan

 

[ptoo30]

Re: DRC Rule Question

m1 is lower level metal in the cell, we use m1 as interconnection between transistors so minimum line and space is needed.
m2-m5 are interconnect between cells and do not need so small design rule. m6 is top layer, we use it for VDD VSS and inductor, low resistance is good.

 

[RC13]

DRC Rule Question

for tsms or others foundry, metal width is decided by reliablity actually (resistivity, electrical etc. is fixed once the material is choosen), normally ten years for interconnect is required. m1, m2-m5, m6 has different thckness, thus, different width is required.
this is from process point of view, not from design/layout etc...

 

[Raptor]

Re: DRC Rule Question

i understand that the widths are process dependent but the arguement is why not keep m2-m5 also to minimum width(i.e equal to m1 width) which will reduce the routing area and thus reduce the die size. Why keep m2-m5 equal and change only m1 and m6. A detailed explanation would be a gr8 help

 

[xinsu]

DRC Rule Question

This is a process problem,and I think foundry can explain it clearly.

 

[RC13]

DRC Rule Question

m2-m5 has to be wider as are build after the first CMP, while m1 is not, thus for higher yield m2-m5 is made wider. m6 normally is for current RFIC requirement. if only digital circuit, only m1-m4 is used for synthesis routing (m6 opt out for cost reason), m5 is then used to deal with the antena problem at the final stage.

 

[ptoo30]

Re: DRC Rule Question

i think the reason why M2-M5 design rule is looser than M1 is ;
even we use CMP, M2-M6 has some up and down beneath them.
and M2-M5 are used for Vdd Vss considering reliability.
for M1 thickness is smaller than M2-M5 so etching M1 is easyer than M2-M5 it brings to us the precise design rule
i think only M1 is considered to avoid antenna phoenomina not M5 or M6

 

[mario1980]

Re: DRC Rule Question

Hi,

In almost all technologies, the top metal is thicker, because in large IC's it is used for power distribution. I think below .18 um we are talking ( in general ) about copper interconnect for all metals, and Al wires for top metal (easier to do, cheaper).
About M1, all I can say is that it helps you a lot in layout, if it's smaller in width.

Regards
mario

 

[fixitnow]

Re: DRC Rule Question

Hi

i think that the real problem is the not ideal PLANARITY of the structure.
Meanwhile we think at a CMOS circuit as a planar layout, is a matter of fact that a lot of layer are involved into the construction of the circuit elements. As a consequence, in a Si-based tech, over the device layer there is a passivation layer of Silicon oxide and the contact hole has to be opened in the oxide to connect the device and the M1 wire. Between each M layer and the next M layer, there is also an insulating oxide layer. But raising to the last layer, the planarity will be lost! (Due to the presence of several metal wires in the previous layers). As a consequence, to grant connection and wire integrity, all the metal over the M1 has to be wider... because they have to "walk" along a non planar surface... but also they have to be thicker, to prevent wire corruption over the "stairs" that they have to cross through.