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provides a feedback path, whats your level of engineering understanding, i'm not sure how technical i can get in explaining this, are you familiar with root locus or nyquist plots?
T7 and T8 are supposed to work as a current source,to bias the input pair without losing input commond mode range due to voltage drop in Rtl.
I am curious about T13 T14 T11 T12.
In pair t13 and T14 one can do a 1:N mirror, and then have N times more current
in T11, where again one can do 1:K mirror and get N*K times more current,
but I don't see the reasoning there. One can have a different supply (higher voltage?) for the pair T11-T12, but I see a much reduced headroom for T13.
Why you said "T7 and T8 are supposed to work as a current source,to bias the input pair without losing input commond mode range due to voltage drop "
Can you explain it more ?
And what is the gain of the amp (T1,T2,T3,T4,T6,T7,T8)?
I still can 't understand why the RTL increase the stability .
My analysis is as below.
I suppose VT2_G( voltage of the gate of T2) decrease, and VT8_D decrease, and the current from left to right flow through RTL will increase, and IT2D decrease, and IT3D increase, and IT4D increase, so VT5_G increase, IT5D decrease,IT13D and IT14D decrease, IT11D decrease, IT12D decrease. Finally, VT2_G decrease.
So it's positive feedback. If something is wrong in my analysis, please tell me, thanks.
The added R is called source degenarated resistor, it will reduce the gain of differential pair, and increase it's input range. Reduce gain will increase stability too.
But the circuit is still 2 pole system, some kind of compenstaion is needed except u make the gain of first stage very low (i.e. the non-domainant pole far away ur dominant pole).
But if there is no RTL , the gain will be more samller for the high output R
of current source . So I think the RTL will increase the stability by decreasing
the gain is wrong !
Had u run the simulation of that amp ?
What's the phase margin & DC gain ?
I don't understand why the gain will be larger without RTL?
Can u show us ur simulation of derivation ?
If there is no the RTL , the transconductance will be :
Gm = gm /1 + gmro
where gm is the transconductance of the input device, ro is the output
resistor of the current source .
For ro is very big , t
Gm = 1/ro
But if there is RTL ,
then
Gm = gm/[1 + gm(RTL/2] = 2/RTL
So if there is no the RTL , the gain should be small .
If there is no the RTL , the transconductance will be :
Gm = gm /1 + gmro
where gm is the transconductance of the input device, ro is the output
resistor of the current source .
For ro is very big , t
Gm = 1/ro
But if there is RTL ,
then
Gm = gm/[1 + gm(RTL/2] = 2/RTL
So if there is no the RTL , the gain should be small .
Why the Gm of differential pair without RTL is 1/ro ?
if it was true , then u will always get output gain as Gm*ro=1 ?
The Gm should be equal to gm , such that without RLT ur first stage should
have gain gm*ro !
without RTl means you should replace this resistor with a short line.
and it is a virtual ground at this point for diffrecial circuit
then you should recalculate you Gm
fanrong said:
If there is no the RTL , the transconductance will be :
Gm = gm /1 + gmro
where gm is the transconductance of the input device, ro is the output
resistor of the current source .
For ro is very big , t
Gm = 1/ro
But if there is RTL ,
then
Gm = gm/[1 + gm(RTL/2] = 2/RTL
So if there is no the RTL , the gain should be small .
T1 T2 T3 T4 are standard differential input with current mirror load.
if RTL is zero, then T7 and T8 are two current sinks in parallel. If RTL is non-zero then it's also a standard configuration, and the fact that the bias currents do not go through it keep the input common mode range unchanged.
T5 is a standard second-stage, common source. The load of T5 is not directly
TCL, which would be the standard, but T13 and T14. The way they are connected
the input resistance looking from the drain of T5 into T13 is 1/gm + (N+1)*Ro,
where Ro is the output resistance of TCL. The N is the multiplication factor of the mirror. There's no net increase by doing this, since the current in TCL is increased also by (N+1) , so its Ro was divided by (N+1). Adding T13 and T14 has then another function.
In small signal, it copies current variations in T5 to T11, and T11 copies it to the output with T12. One could then multiply currents by N and then by K in these two mirrors, and use a different supply (higher voltage?) at the output.
The problem is, as already pointed out, that the feedback back to T2 seems to be positive. If T12 sources current into the resistive divider the voltage there will rise, but if if does not then the node will fall to some voltage between the external ground (where ZL is) and VSS. consider TCL a short to ground , and notice that the drain of T5 rises and falls together with the output, to see that the connection
back to T2 makes the feedback positive.
What is the purpose of the circuit, in the patent?
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