why the size dont match???

[fahim1]

hi
this is my code ,and i dont get why the size of this vectors dont match??
i put ?? infront of the vectors that dont match.
all vectrs are std_logic_vectors.
i would appreciate if some one help me
tnx

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.std_logic_unsigned.all;
    ----------------------------behavioral---------------
    entity mdbooth2 is
    port(mpcd,mplr : in std_logic_vector(3 downto 0);
     result : out std_logic_vector(7 downto 0);
     clk : in std_logic);
     end mdbooth2;
 
     architecture Behavioral of mdbooth2 is
    signal tmplr : std_logic_vector(4 downto 0) :=  mplr & '0';
    begin
    process(clk)
    variable p1,p2 : std_logic_vector (7 downto 0) := "00000000";
    begin
    if(clk'event and clk='1') then
    case tmplr(2 downto 0) is
    when "000" =>  p1 := "00000000" ;
    when "001" =>  p1 := "0000" & mpcd;
    when "010" =>  p1 := "0000" & mpcd;
    when "011" =>  p1 := "000"  & mpcd & '0';
    when "100" =>  p1 := '0' & not(mpcd) +1;
    if (p1'length = 5) then p1 := "111" & p1 ;   --??
    elsif (p1'length = 6 ) then p1 := "11" & p1;   --?
    end if;
    when "101" =>  p1 := not(mpcd) +1;
     if ( p1'length = 4 ) then p1 := "0000" & p1 ;  --?
    elsif ( p1'length = 5 ) then p1 := "000" & p1;   --?
    end if;
    when "110" =>  p1 := not(mpcd) +1; 
    if (p1'length = 4 ) then p1 := "0000" & p1 ;   --?
    elsif( p1'length = 5 ) then p1 := "000" & p1;   --?
    end if;
    when others =>  p1 := "00000000";
    end case;
     result <= p1 ;
    end if;
    end process;
    end Behavioral;

---

 

[TrickyDicky]

P1 has a length of 8 bits, and will always have a length of 8 bits. So it will never be 4 or 5 bits in length

 

[fahim1]

P1 has a length of 8 bits, and will always have a length of 8 bits. So it will never be 4 or 5 bits in length

if i have a vector of 4 bit named m and I want to assign m+1 to another vector p, i dont know whether m+1 is 4bit or 5bit ,what should i do??
how shuold i put the length of p??

 

[TrickyDicky]

But you know the size of the bus, because you declared it. You always know the width. It does not change dinamically.

 

[fahim1]

if i defined it 4 bit the sum maybe 5bit ,and if i defined it 5 bit the sum maybe 4bit.:bang:
in both ways it maybe wrong.

 

[ads-ee]

You're code doesn't even make sense, e.g.

'0' & not(mpcd) +1;
    if (p1'length = 5) then p1 := "111" & p1 ;   --??
    elsif (p1'length = 6 ) then p1 := "11" & p1;   --?
    end if;

if we consider not(mpcd) to be "1111" then adding 1 results in "10000" it can never be more than a 5-bit result, therefore the check for a 6-bit result is useless.

I'm not even sure what you are trying to accomplish, I originally thought you might be trying to do 2's complement math, but then I noticed the implementation is wrong, so now I have no clue what you want.

 

[fahim1]

You're code doesn't even make sense, e.g.

'0' & not(mpcd) +1;
    if (p1'length = 5) then p1 := "111" & p1 ;   --??
    elsif (p1'length = 6 ) then p1 := "11" & p1;   --?
    end if;

if we consider not(mpcd) to be "1111" then adding 1 results in "10000" it can never be more than a 5-bit result, therefore the check for a 6-bit result is useless.

I'm not even sure what you are trying to accomplish, I originally thought you might be trying to do 2's complement math, but then I noticed the implementation is wrong, so now I have no clue what you want.

i write it wrong the correct is

when "100" =>  p1 := ( not(mpcd) +1)&'0';
  if (p1'length = 5) then p1 := "111" & p1(4 downto 0) ;   --??
  elsif (p1'length = 6 ) then p1 := "11" & p1(5 downto 0);   --?
  end if;

i want to have -2*p1 :first 2's complement and then shift to left
if i add 1111 whith 1 it will be 5 bit and after shift it is 6 bit

 

[FvM]

You misunderstand the meaning of the 'length attribute. It only delivers the previously defined size of a vector. It has nothing to do with the actual signal value.

Similarly the size of an expression is not varied depending on the data value, it's determined statically. In some cases an expression, e.g. a "+" operator can involve an overflow so that the expected result can't be represented by the left hand side of the assignment.

Instead of checking the 'length attribute, you may want to check the result bits of an assignment.

 

[fahim1]

You misunderstand the meaning of the 'length attribute. It only delivers the previously defined size of a vector. It has nothing to do with the actual signal value.

Similarly the size of an expression is not varied depending on the data value, it's determined statically. In some cases an expression, e.g. a "+" operator can involve an overflow so that the expected result can't be represented by the left hand side of the assignment.

Instead of checking the 'length attribute, you may want to check the result bits of an assignment.

It only delivers the previously defined size of a vector. It has nothing to do with the actual signal value.

what do u mean by the previous size of vector?if A is 4 bit and some operation execute on on A,and the new valuE of A is 6 bit THE LENGHT attribute still show the 4bit???

is there any code for checking the overflow bit in vhdl?

 

[ads-ee]

there is no such thing as an overflow bit in VHDL. The length of a vector is static. if the length is 4-bits then it will always be 4-bits and trying to assign a result that can become 6-bits will result in an elaboration error, i.e. the RHS of an assignment must be the same size as the LHS.
Your original code:

---

Code VHDL - [expand]
1
2
3
4
5
variable p1 : std_logic_vector(7 downto 0);
p1 := "111" & p1 ;
-- means this:
p1(7 downto 0) := "111" & p1(7 downto 0); -- 3-bits and 8-bits => 11-bit result
                                          -- does not match length of LHS.

---

All calculations should be done with the maximum bit length that can be generated from an addition/subtraction to account for a carry. to add "11" to "11" you would need the follwoing:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
signal a : std_logic_vector(1 downto 0);
signal b : std_logic_vector(1 downto 0);
signal c : std_logic_vector(2 downto 0);
c <= ('0' & a) + ('0' & b);
-- so 011 +011 = 110 (a 3-bit result)
-- and to check if the result had a carry:
if (c(2) = '1') then
  -- stuff to do when there is a carry
else
  -- stuff to do when there's no carry
end if;

---