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Why the setup and hold time is necessary for flop?

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energeticdin

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Hi,

I know the setup and hold time of flop.

Please let me know

Why the setup and hold time is necessary for flop?
I find some explaination that Clock path delay is less than Data path delay, so ther shuld be some setup time?

Plz tell me the device physics level definition? with suitable examples?


Thanks
 

natg9

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Re: Reg: Setup Hold

hi

After all the flops too have transistors
so they take certain time to change from one logic level to the other
this time we give them in terms of setup and hold time

i hope its clear


if still u r in doubt plz let me know
 

energeticdin

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Re: Reg: Setup Hold

Hi natg,

Thanks for ur reply.
Is ther any definiton
like Clock path delay is less than Data path delay, so ther setup time should be ther?

Din
 

natg9

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Re: Reg: Setup Hold

hi energetic

Ya there are constraints
well let me give u concrete data

this PPT will surely help


enjoy buddy :D
 

natg9

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Re: Reg: Setup Hold

I am here to help the world pal

u r welcome
 

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