why the rise ege of the clock is not at 0 in primetime

[tarkyss]

when excute the report_timing in primetime or Design compiler
the start point is a clock signal, but the rise edge of the clock is not at time 0,
it is exactly at the half of the period, but create_clock is from 0.
why
if it is because of propagation delay, i think it is impossible exactly at the half.
i think the clock maybe inverted, but it is hard to check the gate level code.

 

[steven852]

I don't know the answer but you may try to look at clock uncertainty and crpr (clock reconvergence pessimism removal). These would make clock rising edge be negative when doing retiming or time borrowing adjustment.

If you can, let's know what your discoveries are.

 

[wwfhm2002]

you can report timing will -full_path option to view the clock path.