Why the reset is always kept active low?

[skyismylimit]

dff with active high reset

Can anyone know why the reset is always kept active low???? why cant it be active high ???

 

[XNOX_Rambo]

why reset is chosen as active high

 

[jitendra]

Re: Why reset active low ??

Hi,
One possible reason is the Board design methods. Usually capacitor circuit is used for Power-On-Reset, such that the voltage at reset pin gradually goes to HIGH value. And by this time all reset activity is done.
More accurate answers are welcome.

Regards,
Jitendra

 

[kmorsy]

Re: Why reset active low ??

is it related by any mean to how the design is implemented??

 

[Moof]

Re: Why reset active low ??

For me ,you use inverse logical, becasue the noise. Is less probably that something becames active if it is in high state. But if you use high active, the noise is going to activate your device. My english is not very good, so i hope you anderstand me.

 

[jackson_peng]

Why reset active low ??

i've heard that the PMOS can provide a higher resistance than NMOS.
so reset are kept high to minium the leakage at its load cells

 

[IanP]

Re: Why reset active low ??

So far I haven't found really good reasons why it could not be high?
For example, the 8051 family: the reset is high active .. and no complains about it ..

 

[stormwolf]

Why reset active low ??

I think main about noise, at high the circus noise is small .

 

[pisoiu]

Why reset active low ??

It is only an assumption, but IMHO in older circuit boards, the reset signal had to be distributed among many processors and peripherals reset, flip-flops reset, couters reset, etc. The result is a highly loaded reset line, which is easier to drive by a open collector outputs or a typical pnp-npn output. Since the output transistors in the gnd side can handle high loads better that transistors on vcc side, it was chosen this sollution.

/pisoiu

 

[power-twq]

Re: Why reset active low ??

because in dff, active low reset has more simple logic, that's the reason.

Can anyone know why the reset is always kept active low???? why cant it be active high ???

 

[nemolee]

Re: Why reset active low ??

Because the power is from off to on.
When the power is off, the signal is low.
When the power is rising to high, the signal is rising to high.
When the power is high and stable, then the signal is high.

 

[hock]

Re: Why reset active low ??

The reason is same as why all control signal are active low, and is very simple.
the digital bus is always noisy and most often in try state mode on the transmitter side. the receiver is high impedance mode device.
noise can charge the bus in the range of TTL high and hence you may get a false trigger.
the bus will have a clean low level state only when the Driver pulls it low, and has sufficiently low impedance so as to keep noise pickup very low.

hock

 

[dolby.yang]

Re: Why reset active low ??

it is safe to use reset singnal that active state is low ,because for our board design,

when reset singnal is inactive.reset singnal is high,it is not easy to change this state by other factor like glicth on board.

usually,in our chip has logic circuit to filter reset singnal's glicth.

when reset singnal is active high,this will need a hith performance filter circuit for this singal!

 

[kxchorus]

Why reset active low ??

because in popular DFF's design, the set or reset circuit is implemented by nand gate. If the reset or set is active high, we have to use nor gate or at least add one inverter for these signals.
Nor gate have worse performance compared nand gate (for same area) since its PMOS transistor is in series while nand gate the PMOS is in pararell.

 

[jjww110]

Why reset active low ??

i think the noise is the main reason

 

[kaustubh.pagedar]

Hi,
one reason I can see is noise can affect on signals...
Now if we have active high signal that means most of the time our our rest signal will be LOW.
So any jiiter on the signal can be detected as a reset if we have active high reset.

On other hand if we have active low signal, once RESET is available signal will go low and then come back to high state. So any jitter on signal will not be detected as a RESET and our design will not observe any false RESET.

Please suggest in case I am missing anything....

 

[eld03]

the to avoid reset on glitch. the problem is was more pronounced with TLL logic due to its logic level definition. The only stupid device that made a mistake with active high reset if from intel 8155. they learned their lesson well.