Why the power consumption of cmos is low?

[sachinmaheshwari]

why the power consumption of cmos is low...
i want appropriate answer....n if u can tell me diagramatically it would be better for me to understand

 

[avimit]

Re: cmos

Except CMOS logic, for example TTL logic, or RTL logic, or N-mos logic etc... there is a constant drain of current from pwr to gnd, which 'wastes' power.
However in CMOS logic there is no path for the current to flow from pwr to gnd, unless both n-mos and p-mos are 'ON'. This only happenes while the CMOS gate is in 'transition' i.e going from 0to1 or 1to0. So as long as the input of the CMOS gate is static, there isn't any current drain from pwr to gnd(except leakgae current which is very very small). So there isn't any 'waste' of power.
Hence CMOS is low power.
Hope it helps.
Kr,
Avi
http://www.vlsiip.com

 

[abhaykochhar2]

Re: cmos

thats a perfect answer.. try to read some topics from CMOS VLSI Design from Weste HARRIS.... u will understand it in better way...

 

[kpsai26779]

cmos

Hi sachinmaheshwari,

For CMOS static power consumption is very low, which can be neglected and the total power consumption is almost equal to Dynamic power consumption.

CMOS circuits have high ip impedance so ip current is almost zero so less power is required to supply to drive load

 

[anantha_09]

Re: cmos

ok can any one tell how to calculate power dissipation and propagation delay of cmos inverter

please come out it with clear explanation with expressions and diagrams

thanks in advance