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Except CMOS logic, for example TTL logic, or RTL logic, or N-mos logic etc... there is a constant drain of current from pwr to gnd, which 'wastes' power.
However in CMOS logic there is no path for the current to flow from pwr to gnd, unless both n-mos and p-mos are 'ON'. This only happenes while the CMOS gate is in 'transition' i.e going from 0to1 or 1to0. So as long as the input of the CMOS gate is static, there isn't any current drain from pwr to gnd(except leakgae current which is very very small). So there isn't any 'waste' of power.
Hence CMOS is low power.
Hope it helps.