why the output wave of this op-amp is not symmetric?

[cqmyg5]

op amp out put wave

Hi,

I'm studying a common cascode op-amp with CMFB(vdd=1.8v). I perform a transient simulation by inputing 5mv sine wave, the below figure is the open-loop output wave. why the output is not symmetric? the positive edge is sharp, the negative edge is flat with a little distortion. How to deal with this case?

 

[thuvu]

symmetric opamp

Does the distortion goes away when you lower the frequency?

 

[cqmyg5]

why is op-amp output swing saturated

Does the distortion goes away when you lower the frequency?

No, when I input 100k sine wave, the distortion is still like previous wave.

and when I input 40k sine wave, it still has same result.

 

[borislee]

Lower the amplitude of input and check the shape of output

 

[cqmyg5]

Lower the amplitude of input and check the shape of output

If lower the input amplitude, its output could be beautiful sine wave, both sides are symmetric, maybe it has a tiny lean to left. please check.

I find some output wave in other papers, the wave is symmetric even if the input amplitude is large.

 

[snowball]

This is because of your linear output range is not symmetric.
When you are putting in large signal, you are basically saturating the PMOS and NMOS at the output stage.
When you positive signal saturates the PMOS, your NMOS must be saturated in the same way to be symmetric. Since the PMOS and NMOS are not meant to be identical, even you design the output waveform to look the same, you will still get a big variation when you have different type of input.

 

[cqmyg5]

This is because of your linear output range is not symmetric.
When you are putting in large signal, you are basically saturating the PMOS and NMOS at the output stage.
When you positive signal saturates the PMOS, your NMOS must be saturated in the same way to be symmetric. Since the PMOS and NMOS are not meant to be identical, even you design the output waveform to look the same, you will still get a big variation when you have different type of input.

Thanks! what you mean "different type of input"? different freq. or different amplitude? if a full differential op-amp could not output symmetric, the large output swing is useless, right?

How to design the output waveform to look the same at large input? just for simulation.

 

[willyboy19]

The test/simulation condition of your setup is meaningless: the fully differential OTA is never going to be used in the open-loop structure for linear amplification, exept used as comparators (in which case you don't care about the symmetry of your output at all).

What is really important is that in close-loop configuration in your system, you need to make sure its output swing is symmetrical around its common-mode voltage, provided you have sufficient DC gain to begin with (and bandwidth as well, if AC signal is of your interest).

So all the discussions above can stop now.

 

[MLR67]

Sorry ,
but I didnt see any CMFB in your schematic .
Are you using one ?

 

[cqmyg5]

Sorry ,
but I didnt see any CMFB in your schematic .
Are you using one ?

YES, there's resistor detector CMFB and CM voltage is 0.9v.

 

[MLR67]

Ok ,
may you provide the BW and stability of your CMFB ?
I suppose you have a problem with your CMFB , but I need more informations, because when you decrease the imput amplitude of your signal , disymetry is still there.

 

[cqmyg5]

Ok ,
may you provide the BW and stability of your CMFB ?
I suppose you have a problem with your CMFB , but I need more informations, because when you decrease the imput amplitude of your signal , disymetry is still there.

Thanks!, Actually by decreasing the input frequency, disymetry is still there. but by decreasing the amplitude, the disymetry is gone.

the GBW of the CMFB's op is 15MHz, phase margin is 95 degree.

 

[MLR67]

In this case maybe your problem is slew rate limiting!
In this case one possible solution is to increase resistors of your CMFB.

 

[rfsystem]

Independend of the doubts of others about the usage there is a simple answer to this asymmtry issue.

If the PMOS cascode current source goes out of saturation it has to first recharge the gate/source cap. I guess that the cap of the PMOS is bigger than the NMOS. The effect is stronger for higher frequencies.

Normaly you use the ouput stage only up to the saturation of the cascode. So from nonlinearity aspect the drain/bulk diode of the PMOS and NMOS cascode devices in the normal voltage operating range could have a further small effect. But his could be compensated up to higher orders by additional diode caps.

But if you using a simple diffpair as input this would limit the linearity.