Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

why the minimal channel length is 240nm in .25u technology??

Status
Not open for further replies.

hbchens

Junior Member level 3
Joined
Aug 29, 2004
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
282
why the minimal channel length is 240nm in .25u technology of NCSU_CDK?
Hi guys:
I have drawn an op-amp circuit in the schematic of cadence with the tsmc_03d-technology in NCSU_CDK_1.5.1.Its .tf file is as follows:
"TSMC 0.25u
controls(
techParams(
( lambda 0.12 )
( technology "TSMC_CMOS025_DEEP" )
( metal3Available t )
( metal4Available t )
( metal5Available t )
( metalcapAvailable t )
( sblockAvailable t )
( hvAvailable t )
)
)
"
Why is the lambda=0.12um?Why is the lib default minimal length 0.24um ?Does the minimal channel length should be >=0.25um?
 

hbchens

Junior Member level 3
Joined
Aug 29, 2004
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
282
Can anyboby give me a response?
 

zhaoshibin

Member level 2
Joined
Oct 11, 2006
Messages
43
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,489
I have a same question:Why the wmin is also bigger than the lmin in the CMOS processing?
 

dozy_walia

Full Member level 2
Joined
Jan 10, 2007
Messages
136
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,096
I^^^ Its in PMOS not in NMOSE.. as hole mobility is lower than electrons so PMOS are slower and we use larger width to make them more mobile!
Hope it helps!
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top