Why the long term 1 and 0 number balance affect clock recovery?

[ermai]

As the title,the 1 and 0 sequence number should be balanced to decrease error rate(clock recovery).
I would like to know the principle.Thanks

 

[D.A.(Tony)Stewart]

If there is no DC restore circuit or the data protocol is design to not have DC content then the data average DC level affects the relative slicer level and then edge jitter can occur when bandwidth or slew rate limited and then the edges can become skewed and thus the edge tracking clock recovery can have phase error.

This does not apply to a NRZ method of data protocol but may be corrected using RLL codes that are inverted periodically to remove DC.

There are many different baseband data modulation methods or protocols and also many clock recovery methods. You may be reading about ones where the data can be AC coupled and rely on an even balance of 1's and 0's

e.g. https://en.wikipedia.org/wiki/8b/10b_encoding