ASIC_intl
Banned
Hi
In design compiler I found after synthesisi the timing is met but the DRC s (max_transition, max_capacitance) are being violated for some of the nets. Why are there DRC violation.
Regards.
In design compiler I found after synthesisi the timing is met but the DRC s (max_transition, max_capacitance) are being violated for some of the nets. Why are there DRC violation.
Regards.