Re: Why the DLL locking range be limited in the range of ...
yes, lock range is determined by characteristic of pd. For example, if the delay between out clk and ref cll is in (0.5T,T), pd will give down signal and increase the delay to T. If the delay between out clk and ref cll is in (T,1.5T), pd will give up signal and decrease the delay to T. But if delay >1.5T, pd will give down signal and decrease delay to 2T, which is a false locking. It is same for delay < 0.5T. Now most DLLs introduce a pd which can avoid the false locking when delay <0.5T. Althrough compliex pfds are introduced to extend lock range to some extent, but it is still a phase detector not a phase and frequency detector as in PLLs, thus lock range is still limited by pd.