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Shielding is for radiated emmisions and radiated immunity. For example, in board layout, you put shields between high speed clock and the data lines because the high speed clock lines might radiate emi noise to other data lines. The shield will just recieve these emi from the clock lines and dissipate them to ground(Vss).
Is emi shielding and electro static shielding are same ?
Wht i meant is shielding in high freequeny Ic layout eg:- shielding of Differential pair input in ADC layout.
Im not sure if both shieldings are the same in IC design. But in board level, it is different.
I am not also familiar with ADC layouts, but as what ive mentioned on the previous note, shields should be connected to ground(Vss) becuase it needs to dissipate the noise to ground. It applies to all shieldings, it may be in the board level or IC level.
Shielding is for radiated emmisions and radiated immunity. For example, in board layout, you put shields between high speed clock and the data lines because the high speed clock lines might radiate emi noise to other data lines. The shield will just recieve these emi from the clock lines and dissipate them to ground(Vss).
Shielding is done in a different way as far as analog layout is concerned. It is not done for the clock lines but we shield the data lines. It will be similar like we insulate a electrical wire.
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Added after 2 minutes:
JoannesPaulus said:
It does not really matter if you connect the shield to VDD or VSS, you just need to connect it to a low impedance net.
sandeep_torgal, I believe (and I have measurements to prove it) that in principle it doesn't matter if you use VDD or VSS as your shield. As I said, it just as to be a low impedance net. In a single supply system, the current taken from VDD will also flow on VSS. The difference is that VSS might have more bond wires and has surely a nice ground plane off-chip.
We should tie the shield to VDD/VSS depending wheteher the current is source or sink. This will inturn help to reduce the cap between the data line to the shielding lines.
Correct me if am wrong or if there are other opinions.
I believe you are confusing shielding and decoupling. I agree with you that if you have, for instance, the gate of a pmos in a current mirror you might want to decouple it with respect to VDD and the gate of an nmos wrt VSS but this is not shielding.
What if you want to "protect" the input signal of your ADC from the clock? Is it sinking or sourcing current? Neither.
In this case you want to have a line that runs parallel to your input signal - between your input signal and the clock - and connect them to either VDD or VSS. Now you are shielding the input signal.
There is no confusion as to the shielding and de-coupling.
Let me know if you ever shield clock lines ? Why not? Its due to the coupling cap because of shielding.
For protecting the input of your ADC from clock, we sheild the input and tie the shield to ground. Ground is more preferred as we may not route the VDD powerlines all over.
I usually do not shield clock lines (they are the aggressors to my analog signals) for the exact reason you mention: the shield might load the clock unnecessarily - and therefore increase the power consumption. I only shield important analog signals (i.e. input signals, bias lines...).
I agree with you that VSS is probably easier to use than VDD.
if you use the ptap on a p-substrate, you must connect to VSS, if you use NWELL and ntap(which make the size bigger) as guard ring, it must be connected to VDD.
if it's metal, yeah, I agree that the VSS is uaually more stable and available.
Shielding is required to protect the critical signals from the noisy signals.
Usually,we shield the critical signals rather than the clk signals as they increase the load on clk signal.
And it's better to connect the shielding lines to VSS as it's more stable than the VDD and it's a low impedence path.
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