why parasitic delay only calculate for falling case?

[anhnha]

Could anyone explain why "parasitic delay" in VLSI only calculate falling case not rising?

 

[SIDDHARTHA HAZRA]

Hi anhnha,

Parasitic delay should effect both during rising and falling. Say you have two inverters (one driving the another). Now if we have a parasitic cap from the intermediate net to ground then during rise, the charging time will increase and during fall the discharging time will also increase. You can replicate some parasitic RC in your schematic using ideal devices and check their effect.

But again can you give us the reference from where you are quoting that parasitic RC effects only falling edge.

Hope this helps ...

 

[anhnha]

Thank you. I drew that conclusion because all reference I had only calculates falling parasitic delay. That is really confusing.

 

[erikl]

... all reference I had only calculates falling parasitic delay.

I guess this pertained to NAND or other gates with parallel transistors in the logic one branch and serial transistors in the logic zero branch? For such gates the falling delay usually is the worst case.

 

[SIDDHARTHA HAZRA]

Hi anhnha / erikl,

Agreeing with erikl ... but parasitic delay will have effect on both rising & falling delay...