I agree, that the fault is apparently already present in the Protel design. I scaled cam1.drl to 50% and got partly reasonable drill sizes. There are however several details that aren't manufacturable as is, e.g. multiple drills in a pad. I also don't understand, why there are 14 different drill files have been produced, most of them empty. The four containing data are almost identical, except for an obviously erratic drill in a SMD pad.
The PCB outline is apparently missing from the gerber plots, it would be expected in *.gm15 according to Protel/Altium standard.
I must add, that I'm no used to operating Protel with imperial (inch) units, the drill size confusion may be related to it.
To make us understand the nature of the problem, you should possible show a screenshot of the layout, or post 68_design.pcbdoc.
P.S.: To add a more general comment: I seriously doubt, if the design will work reliably with the present supply and ground wiring and effectively no bypass caps near to most logic and memory ICs. It's also strongly recommended to use wider traces for power supply. When making logic circuits on a two-layer PCB, I would always try to wire a least ground and possibly vcc in a grid topology.