Why OCR1A=0x00; still generates a PWM?

[kunal5959]

I am getting a small Duty cycle generated when i set OCR1A to zero and ICR1=3667(which is 500Hz) for TIMER1 of ATMEGA128A..
According to my understanding if i set all the COM1A1, CS and WGM registers correctly for FAS PWM mode OCR1A =0x00; should generate a PWM such that Dutycycle =0/3667 *100..this implies zero duty cyle...why is there always a small dutycycle being generated??

 

[KlausST]

Hi,

i don´t know why this is.

But in datasheet you will find this:

The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output
will be a narrow spike for each TOP+1 timer clock cycle.

So it is documented.

Klaus