why not use one big mos cap? why use large capacitor by parallel unit cell?

[seungmoon]

u said
"In general, in the chip spare space we add moscap(gate connect to one power rail, and source-drain connect to the other power rail) for decoupling as moscap has most unit capacitor?'

why do we use unit capacitor ?

for example, why not use one big mos cap? why use large capacitor by parallel unit cell?

 

[erikl]

why do we use unit capacitor ? why use large capacitor by parallel unit cell?

To achieve high accuracy results from simulation analysis. Unit caps are well characterized.

why not use one big mos cap?

You can do this if simulation accuracy is less important than a high cap value.

 

[checkmate]

I don't think accuracy is required for decoupling caps, just spam as much as possible.
The only reason I can think of, other than the obvious process max-size limitations,
is that smaller MOScaps can also be used for parking components as well.

 

[varunkant2k]

for example, why not use one big mos cap? why use large capacitor by parallel unit cell?

Parallel unit cells reduces the ESR of the cap and approaches ideal cap behavior ( without loss)

 

[dick_freebird]

MOS capacitors, especially at low Vgs, have very poor series
resistance (channel R and gate R is in series with C).

But you want to have a look at how little R you can stand,
a super high quality capacitor may resonate with supply
bondwire L. A little bit of R may be quieter internally than
none, especially if your resonant decoupling f just happens
to be near a significant clock frequency or f/2 (the IDD
spikes happen on every edge). Supply ringing phase-in,
phase-out can create strange jitter behaviors and so on.