why negative hold time?

[chintalaudaykumar]

negative hold time

hi,
In .lib files of the TSMC the hold time is in negative, what is the reason?
what does it mean?

thanks in advance,

 

[gajanans]

negative or positive hold time asic

Hi,

The setup and hold will be calculated taking clock signal as reference signal. So, setup will be the time of arrival of data before clock edge where as hold will be time after clock edge till data is stable. In simple words
setup and hold will be ( clock edge - data edge ). So, in general case setup will be positive and hold will be negative.

Hope this answers your query.

 

[boardlanguage]

what is a flioflop ?

In normal (Primetime/Design Compiler) timing notation, a positive-hold time +X ns indicates that the flop's D-input must be held steady until +X ns after the launching clock-edge.

If the hold-time is negative -X, then the time-reference is reversed. In other words, -X means the data-signal only needs to be held steady until -X ns before the clock-edge. This sounds counter-intuitive, but it's actually common on muxed-scanflops (these are flipflops which have integrated Scan-In, Scan-Data, Scan-Out, and Scan-Enable ports.)

Another way to look at it is the flipflop has extra 'combinational logic' hidden inside the cell, between the visible ports (D, CK, Q), and internal state-element. Since the comb-logic always has a propagation-delay >0, this forces the setup&hold values to be shifted away from the launching clock-edge (CK.) Net result, the setup/hold values move "left"...

-5 -4 -3 -2 -1 0 1 2 3 4 5
|-------> hold-time (+X=4)

In the above diagram, if the hold-time keeps moving past the origin (0), so that it ends up on the left-side of the origin, then resulting hold-value is negative.

 

[rjainv]

negative thold

Another way of putting it is,

say you had a conventional flop that you are used to seeing with positive hold time. Now you added buffer on data path with delay value equal to hold time. So at the input of this new buffer, the hold time requirement is zero with respect to the clock edge at flop input. Further increase in delay of buffer will make hold time requirement negative. Pull this buffer into the flop, and you get negative hold time at the flop input.

 

[ljxpjpjljx]

negative hold in flops

with the process change, the negative hold time is possible!

 

[snr_vlsi]

negative hold time flop

Negative hold time is generally seen where a delay is already added in the data path
inside the flop.

Assume the flop which foundry gives us as library part has ports named as CLK-port,
Data-port. Now treat this as a wrapper. Inside this we have the real flop whose
ports are CLK-in, data-in. CLK-port is connected directly to CLK-in, Data-port goes
through some delay element (either buffer or routing whatever) to Data-in. So even
if the actual flop has hold requirement of say 0.2ns, if the data delay element
value is 0.5ns, the library will give spec as -0.3ns HOLD requirement for the above
flop. This signifies even if the data changes 0.3ns before CLK, it can be still
latched as the actual flop will still meet 0.2ns HOLD. (data changes after 0.2ns
from clk change).

 

[ASIC_intl]

holdtime for a flop

In case bufferes are added in data path hold time will go negative. What is the necessity of adding these buffers in datapath?

Do the designers target to design a flop with negative hold time intentionally? What are all the benefits of negative hold time?

What is the reason to make the datapath slow by adding buffers during fabrication if designers do not want to design a flop with negative hold time and if designers hand over the charecteristics of the flop to the foundry with a zero or positive hold time?

Is it all the flops in the TSMC library has negative hold time?

Added after 1 minutes:

How can process shift make the hold time negative?

Added after 28 minutes:

Set-up time can be negative theoretically. Is there anyone who has seen the set up time to be negative in any library?

 

[gajanans]

data path delay negative

One of the reason for having buffers in data paths is to provide isolation b/w master and slave latch. It is important to make sure there is no reverse path from q to d . Another reason would be it improves the slew

 

[rjainv]

what is hold time negative

Usually negative hold time is not intentional, but because datapath delay got increased because of Scan mux on D or some other reason like balancing internal delays.

 

[ASIC_intl]

hold time violation negative

Hi gajanans

We in digital circuits use only flipflop. Inside a flipflop there is master and slave latches present. There is no buffers generally present inside a flioflop for isolation b/w master and slave latch.

What is the necessity of this isolation?

Do u want to mean any othe master-slave configuration when you write about isolation b/w master and slave latch.


How can u improve slew by putting buffer?

Hi rjainv

What is the necessity of balancing internal delays? How are they generally balanced? What are the paths that are balanced for internal delays?

I find negative hold time in most of the libraries. The design of a flipflop (those are present in the library) for positive hold time can be made taking care of delays for Scan mux on D and any other reason that makes the hold time finally negative. So probably the negative hold time is intentional. Probably the flops are designed to make the hold time negative. If it is not intentional, the design of the flop could also be done to make the hold time positive taking care of the reasons that may make the hold time negative. What are the comments for the above thinking?


What are the benefits of negative hold time.

 

[jarodz]

hold time library

Hi ASIC_intl,

The buffers must be insert to clock path o make the hold time of the scan FF to be positive. The area increase. In the asic, after clock tree synthesised, there will be clock skew between FFs. For short data path delay, the hold violation may occur due to the clock skew. The negative hold time of FF may reduce these hold time violations.
The scan shift paths usually the hold time violatoins path due to clock skew.

Sincerely,
Jarod

 

[gajanans]

how to implement negative hold time

Hi,

Isolation is necessary in flops if there is use of transmission gates ( pass transistors ). In such case, there is a possibility of a reverse path from slave latch to master latch.

Buffers definitely improve slew. Say, A high slew signal drives a higher drive buffer , we can expect a high current charging/discharging the o/p cap which improves the slew.

 

[sowmya005]

output hold time in flip flop

Hi friends,
I have a problem of calculating hold time.
A flipflop has a combo of delay td in the data path and
a combo of delay tc in the clock path.
If this becomes a new flop with input of the combo in the data path becomes new D pin and input of combo in clock path becomes new clock pin,
the output Q remains same.
what is the relation between the old hold time and the new hold time?
Can we find the relation between the old setup time and the new setup time also?

 

[sages]

thx to above answers. it seems possible that the intrinsic hold time is negative just because the inner combinational logic. Is that alright?

 

[dftrtl]

Yes It is right thing

 

[Prashanthanilm]

Tinitial is the time delay introduced by the combinational logic sitting before the first transmission gate and TTX is the time taken for the transmission gate to switch ON or OFF after the CLK and CLK BAR is given.
if Tinitial > TTX ->-ve Hold time
if Tinitial = TTX ->0 Hold time
if Tinitial < TTX ->+ve Hold time

- - - Updated - - -

Can anyone explain me about negative set up time?