what is a flioflop ?
In normal (Primetime/Design Compiler) timing notation, a positive-hold time +X ns indicates that the flop's D-input must be held steady until +X ns after the launching clock-edge.
If the hold-time is negative -X, then the time-reference is reversed. In other words, -X means the data-signal only needs to be held steady until -X ns before the clock-edge. This sounds counter-intuitive, but it's actually common on muxed-scanflops (these are flipflops which have integrated Scan-In, Scan-Data, Scan-Out, and Scan-Enable ports.)
Another way to look at it is the flipflop has extra 'combinational logic' hidden inside the cell, between the visible ports (D, CK, Q), and internal state-element. Since the comb-logic always has a propagation-delay >0, this forces the setup&hold values to be shifted away from the launching clock-edge (CK.) Net result, the setup/hold values move "left"...
-5 -4 -3 -2 -1 0 1 2 3 4 5
|-------> hold-time (+X=4)
In the above diagram, if the hold-time keeps moving past the origin (0), so that it ends up on the left-side of the origin, then resulting hold-value is negative.