why need to avoid using any latches in my design?

[realtek]

does intel use latch based design

If your circuit is asy circuit
maybe use latch is a good way to perform asy circuit design
but be sure to check if your coding style can be accepted by synth
(such as DC)
if DC not synthesis your RTL as latch
then set synopsys translate off to this latch module when synthesis
use gate level to design the latch which you need

It's not absolute that can not use latch in design.

 

[omara007]

circuit design digital stopwatch tenth thousand

if the latch is mandatory in my design , just like in the case of designing a stop-watch for example .. here the trigger that fires counting has to be independant from the clock .. i guess it can't be a FF .. except if my operating clock's frequency is real high, and the counting would start at the the next clock edge after triggering (where the time here between triggering and the next edge may be in milliseconds or even less) .. here the error would be relatively small ..

BUT .. what if I want the error to be ZERO .. here i have to use a latch ! .. so, would there be any conflict between using latch in my design and the synthesizability .. and JTAG testing ? ..

Is there any other solution to how can one implement the accurate counting of the stop-watch ?

 

[xiongdh]

why latches are not prefered in asic design

can someone give more explation about latches lead to difficult of DFT? for latch can also be scaned by replaced by LSSD.

 

[eexuke]

the problem of latch in dft

I have written a short page about "cycle borrowing" in latch. Hope it can be help.
Refer to the attachment.

 

[elvishbow_zhl]

how to avoid latches in design

but I think latches also have some extra functions to use.
In gated clock circuits latch is useful sometime.
So there is no absolute just your control.

 

[omara007]

latch design avoiding

One good question .. should we never ever use latches ? or we can use latches but under conditions ? ..
what if I have something like that stopwatch that I have to use latch in ! .. does readily availble stopwatches in the market have latches or something else !
what's the exact ptoblem that latches generate with DFT ?

 

[tom123]

avoid latch

because the timing analysis for latch is harder than DFF.

meanwhile, DFT for latch based design is also difficult than

DFF based design.

DFF is edge triggered, but latch is level sensitive,

the former is less sensitive to noise than the latter.

RMM 5.5.2 avoid using any latches in your design.
Can anyone tell me why need to avoid latches?

 

[omara007]

how to avoid latch

I heard that if ur design is fully based on latches only, then there is no problem in any step in the synthesis to backend implementation .. some people say that Intel prefers this, and for sure experiences no problem in its DFT