hello manivannam,
MTCMOS tech is the latest one to reduce leakage power , there many papers and publications related to this topic. well in short i can give u the following points ,
1) In MTCMOS tech. a cluster of cellls are connected to through high Vt Nmos, we can say this as power gating
2) a high vt NMOS r PMOS can be inserted in a non critcal path.
3) the performance of the ckt may change if this is implemented in critical path as it takes soem time to turn on.
jan rabeay books explains very clear abt this .. and many IEEE papers by anantha chandrakasan ..
so u if u need any papers let me know .. i am presently working with leakage power ..
suresh