Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

why lib hold time is -0.0012

Status
Not open for further replies.

bradyue

Member level 2
Joined
Jan 18, 2008
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,603
why could lib hold time could be a negative?
How do clock slew and data slew effect the register hold time ?
 

In fact the hold time of a flip-flop will be positive, but if the library designer put a delay cell before the D pin, then see from the D_external pin, the hold time will be negative, but iif you see from the D pin, the hold time will also be positive.
For example: if a flip-flop's hold time requirement is 0.5ns, then if you add delay cell of 1ns before the flip-flop D input, then see from the input of the delay cell, the flip-flop's hold time will be -0.5ns, bu if you see from the D pin of the flip-flop, the hold time is also 0.5ns.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top